Change: of DDR Unified memory architecture Bandwidth performance: 22.4 GB/s memory interface bus bandwidth 256 GB/s memory bandwidth to EDRAM 21.6 GB/s front-side bus GPU specs (graphics)Custom ATI graphics processor Specs: 500MHz processor 10 MB of embedded DRAM 48-way parallel floating-point dynamically scheduled shader pipelines Unified shader array Performance:   View changes from previous version. (Word count: 443)

Change: There were only format changes (bold, italics, etc.) in this version. See this version for details. (Word count: 434)

Change: There were only format changes (bold, italics, etc.) in this version. See this version for details. (Word count: 434)

Change: Detailed system specifications: CPU (processing):Custom IBM PowerPC-based CPU - designed by IBM based on their Power Architecture Specs: Three symmetrical cores, each running at 3.2 GHz Two hardware threads per core for a total of six hardware threads VMX-128 vector unit per core; three total 1 MB L2 cache   View changes from previous version. (Word count: 434)

Change: Detailed system specifications: CPU (processing):Custom IBM PowerPC-based CPU - designed by IBM based on their Power Architecture Specs: Three symmetrical cores, each running at 3.2 GHz Two hardware threads per core for a total of six hardware threads VMX-128 vector unit per core; three total 1 MB L2 cache   View changes from previous version. (Word count: 437)

Change: § The advanced structure dramatically reduces parasitic resistance and capacitance throughout the memory array, thus minimizing both random access time and power consumption§ The low parasitics ensure stable operation under low operating voltage § The low-voltage, fast-access features of the NEC Electronics process results in very high eDRAM speeds   View changes from previous version. (Word count: 529)

Change: Created by wetpaint Feb 19 2006, 1:07 PM EST for: no reason given